Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve
Journal of Systems Architecture: the EUROMICRO Journal
Hardware architectures for the Tate pairing over GF(2m)
Computers and Electrical Engineering
Arithmetic Operators for Pairing-Based Cryptography
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
FPGA and ASIC implementations of the ηT pairing in characteristic three
Computers and Electrical Engineering
A flexible processor for the characteristic 3 ηT pairing
International Journal of High Performance Systems Architecture
SPA resistant elliptic curve cryptosystem using addition chains
International Journal of High Performance Systems Architecture
A new bit-serial multiplier over GF(pm) using irreducible trinomials
Computers & Mathematics with Applications
Side channel attacks and countermeasures on pairing based cryptosystems over binary fields
CANS'06 Proceedings of the 5th international conference on Cryptology and Network Security
Instruction set extensions for pairing-based cryptography
Pairing'07 Proceedings of the First international conference on Pairing-Based Cryptography
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Identity-based cryptography uses pairing functions, which are sophisticated bilinear maps defined on elliptic curves. Computing pairings efficiently in software is presently a relevant research topic. Since such functions are very complex and slow in software, dedicated hardware (HW) implementations are worthy of being studied, but presently only very preliminary research is available. This work affords the problem of designing parallel dedicated HW architectures, i.e., co-processors, for the Tate pairing, in the case of the Duursma-Lee algorithm in characteristic 3. Formal scheduling methodologies are applied to carry out an extensive exploration of the architectural solution space, evaluating the obtained structures by means of different figures of merit such as computation time, circuit area and combinations thereof. Comparisons with the (few) existing proposals are carried out, showing that a large space exists for the efficient parallel HW computation of pairings.