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Mathematics of Computation
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Parallel Hardware Architectures for the Cryptographic Tate Pairing
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Efficient pairing computation on supersingular Abelian varieties
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Efficient tate pairing computation for elliptic curves over binary fields
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Hardware acceleration of the tate pairing in characteristic three
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Efficient hardware for the tate pairing calculation in characteristic three
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
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Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
FPGA and ASIC implementations of the ηT pairing in characteristic three
Computers and Electrical Engineering
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The ηT pairing is an efficient method for the calculation of the Tate pairing. In this paper, we describe the hardware implementation of the ηT pairing on a supersingular elliptic curve of characteristic 3. All characteristic 3 operations required for the computation of the pairing are outlined in detail. We describe how the required extension field operations can be performed in terms of subfield operations, many of which can be computed in parallel in hardware. The hardware architectures required for pairing computation are also described. An efficient and reconfigurable processor utilising these hardware architectures is presented and discussed. The processor is highly reconfigurable and can easily be tailored for a low area implementation, or for a high throughput implementation or for a desired balance between the two. Results are provided for various configurations of the processor when implemented over the field F397 on an FPGA.