Hardware acceleration of the tate pairing in characteristic three

  • Authors:
  • P. Grabher;D. Page

  • Affiliations:
  • Institute for Applied, Information Processing and Communications, Graz University of Technology, Graz, Austria;Department of Computer Science, University of Bristol, Bristol, United Kingdom

  • Venue:
  • CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
  • Year:
  • 2005

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Abstract

Although identity based cryptography offers many functional advantages over conventional public key alternatives, the computational costs are significantly greater. The core computational task is evaluation of a bilinear map, or pairing, over elliptic curves. In this paper we prototype and evaluate polynomial and normal basis field arithmetic on an FPGA device and use it to construct a hardware accelerator for pairings over fields of characteristic three. The performance of our prototype improves roughly ten-fold on previous known hardware implementations and orders of magnitude on the fastest known software implementation. As a result we reason that even on constrained devices one can usefully evaluate the pairing, a fact that gives credence to the idea that identity based cryptography is an ideal partner for identity aware smart-cards.