Exponentiation cryptosystems on the IBM PC
IBM Systems Journal
The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation
IEEE Transactions on Computers - Special issue on computer arithmetic
IEEE Transactions on Computers
Some operators for on-line radix-2 computations
Journal of Parallel and Distributed Computing
Efficient Algorithms for Pairing-Based Cryptosystems
CRYPTO '02 Proceedings of the 22nd Annual International Cryptology Conference on Advances in Cryptology
ANTS-V Proceedings of the 5th International Symposium on Algorithmic Number Theory
A Scalable and Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)
CHES '00 Proceedings of the Second International Workshop on Cryptographic Hardware and Embedded Systems
A Bit-Serial Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)
CHES '01 Proceedings of the Third International Workshop on Cryptographic Hardware and Embedded Systems
Hardware Implementation of Finite Fields of Characteristic Three
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Guide to Elliptic Curve Cryptography
Guide to Elliptic Curve Cryptography
Architectural Support for Arithmetic in Optimal Extension Fields
ASAP '04 Proceedings of the Application-Specific Systems, Architectures and Processors, 15th IEEE International Conference
Hardware and Software Normal Basis Arithmetic for Pairing-Based Cryptography in Characteristic Three
IEEE Transactions on Computers
Parallel Hardware Architectures for the Cryptographic Tate Pairing
ITNG '06 Proceedings of the Third International Conference on Information Technology: New Generations
An Embedded Processor for a Pairing-Based Cryptosystem
ITNG '06 Proceedings of the Third International Conference on Information Technology: New Generations
Efficient GF(pm) arithmetic architectures for cryptographic applications
CT-RSA'03 Proceedings of the 2003 RSA conference on The cryptographers' track
Implementing cryptographic pairings on smartcards
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
Efficient tate pairing computation for elliptic curves over binary fields
ACISP'05 Proceedings of the 10th Australasian conference on Information Security and Privacy
High security pairing-based cryptography revisited
ANTS'06 Proceedings of the 7th international conference on Algorithmic Number Theory
Hardware acceleration of the tate pairing in characteristic three
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Efficient hardware for the tate pairing calculation in characteristic three
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
IEEE Transactions on Information Theory
Designing an ASIP for Cryptographic Pairings over Barreto-Naehrig Curves
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Efficient, secure, and isolated execution of cryptographic algorithms on a cryptographic unit
Proceedings of the 2nd international conference on Security of information and networks
An exploration of mechanisms for dynamic cryptographic instruction set extension
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
| Hi-index | 0.00 |
A series of recent algorithmic advances has delivered highly effective methods for pairing evaluation and parameter generation. However, the resulting multitude of options means many different variations of base field must ideally be supported on the target platform. Typical hardware accelerators in the form of co-processors possess neither the flexibility nor the scalability to support fields of different characteristic and order. On the other hand, extending the instruction set of a generalpurpose processor by custom instructions for field arithmetic allows to combine the performance of hardware with the flexibility of software. To this end, we investigate the integration of a tri-field multiply-accumulate (MAC) unit into a SPARC V8 processor core to support arithmetic in Fp, F2n and F3n. Besides integer multiplication, the MAC unit can also execute dedicated multiply and MAC instructions for binary and ternary polynomials. Our results show that the tri-field MAC unit adds only a small size overhead while significantly accelerating arithmetic in F2n and F3n, which sheds new light on the relative performance of Fp, F2n and F3n in the context of pairing-based cryptography.