Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve
Journal of Systems Architecture: the EUROMICRO Journal
Hardware architectures for the Tate pairing over GF(2m)
Computers and Electrical Engineering
A Coprocessor for the Final Exponentiation of the ηTPairing in Characteristic Three
WAIFI '07 Proceedings of the 1st international workshop on Arithmetic of Finite Fields
Multiplication over Fpm on FPGA: a survey
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
A new bit-serial multiplier over GF(pm) using irreducible trinomials
Computers & Mathematics with Applications
Side channel attacks and countermeasures on pairing based cryptosystems over binary fields
CANS'06 Proceedings of the 5th international conference on Cryptology and Network Security
Instruction set extensions for pairing-based cryptography
Pairing'07 Proceedings of the First international conference on Pairing-Based Cryptography
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In recent times bilinear pairings have been instrumental in the design of many new cryptographic protocols and have provided elegant solutions to existing protocol problems. The ç pairing is one such pairing and is an efficient computation technique based on a generalization of the Duursma Lee method for calculating the Tate pairing. The pairing can be computed very efficiently on genus 2 hyperelliptic curves. In this paper it is demonstrated that this pairing operation is well suited to a dedicated parallel hardware implementation on an FPGA. An ç pairing processor is described in detail and the architectures required for such a system are discussed. Prototype implementation results are presented over a base field of F_2^103 and the advantages of implementing the pairing on the dedicated processor are discussed