A fast algorithm for computing multiplicative inverses in GF(2m) using normal bases
Information and Computation
A remark concerning m-divisibility and the discrete logarithm in the divisor class group of curves
Mathematics of Computation
Low-Energy Digit-Serial/Parallel Finite Field Multipliers
Journal of VLSI Signal Processing Systems - Special issue on application specific systems, architectures and processors
Identity-Based Encryption from the Weil Pairing
CRYPTO '01 Proceedings of the 21st Annual International Cryptology Conference on Advances in Cryptology
Efficient Algorithms for Pairing-Based Cryptosystems
CRYPTO '02 Proceedings of the 22nd Annual International Cryptology Conference on Advances in Cryptology
Short Signatures from the Weil Pairing
ASIACRYPT '01 Proceedings of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
ANTS-V Proceedings of the 5th International Symposium on Algorithmic Number Theory
Low-Cost Solutions for Preventing Simple Side-Channel Analysis: Side-Channel Atomicity
IEEE Transactions on Computers
An Embedded Processor for a Pairing-Based Cryptosystem
ITNG '06 Proceedings of the Third International Conference on Information Technology: New Generations
Efficient pairing computation on supersingular Abelian varieties
Designs, Codes and Cryptography
An Algorithm for the nt Pairing Calculation in Characteristic Three and its Hardware Implementation
ARITH '07 Proceedings of the 18th IEEE Symposium on Computer Arithmetic
Some efficient algorithms for the final exponentiation of ηT pairing
ISPEC'07 Proceedings of the 3rd international conference on Information security practice and experience
Multiplication over Fpm on FPGA: a survey
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Collusion resistant broadcast encryption with short ciphertexts and private keys
CRYPTO'05 Proceedings of the 25th annual international conference on Advances in Cryptology
Hardware acceleration of the tate pairing in characteristic three
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
Efficient hardware for the tate pairing calculation in characteristic three
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Breaking pairing-based cryptosystems using ηT pairing over GF(397)
ASIACRYPT'12 Proceedings of the 18th international conference on The Theory and Application of Cryptology and Information Security
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Since the introduction of pairings over (hyper)elliptic curves in constructive cryptographic applications, an ever increasing number of protocols based on pairings have appeared in the literature. Software implementations being rather slow, the study of hardware architectures became an active research area. Beuchat et al.proposed for instance a coprocessor which computes the characteristic three 茂戮驴Tpairing, from which the Tate pairing can easily be derived, in 33 μs on a Cyclone II FPGA. However, a final exponentiation is required to ensure a unique output value and the authors proposed to supplement their 茂戮驴Tpairing accelerator with a coprocessor for exponentiation. Thus, the challenge consists in designing the smallest possible piece of hardware able to perform this task in less than 33 μs on a Cyclone II device. In this paper, we propose a novel arithmetic operator implementing addition, cubing, and multiplication over $\mathbb{F}_{3^{97}}$ and show that a coprocessor based on a single such operator meets this timing constraint.