Network-on-Chip interconnect for pairing-based cryptographic IP cores

Authors:
Tom English;Emanuel Popovici;Maurice Keller;W. P. Marnane
Affiliations:
Department of Electrical and Electronic Engineering, University College Cork, Ireland;Department of Electrical and Electronic Engineering, University College Cork, Ireland;Department of Electrical and Electronic Engineering, University College Cork, Ireland;Department of Electrical and Electronic Engineering, University College Cork, Ireland
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2011

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Abstract

On-chip data traffic in cryptographic circuits often consists of very long words or large groups of smaller words exchanged between processing elements. The resulting wide cross-chip buses exhibit power, congestion and scalability problems. In this paper, two case study cryptographic IP cores with demanding interconnect requirements are implemented on 65nm CMOS. Lightweight, custom bus-replacement Networks-on-Chip (NoCs) have been developed for both cores. Results show that eliminating the 251-bit-wide cross-chip cryptographic buses dramatically improves the quality of physical implementation. The results have applicability to wire-constrained designs in other domains.