Technology mapping with crosstalk noise avoidance
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Network-on-Chip interconnect for pairing-based cryptographic IP cores
Journal of Systems Architecture: the EUROMICRO Journal
A methodology for the early exploration of design rules for multiple-patterning technologies
Proceedings of the International Conference on Computer-Aided Design
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Due to increasing design complexities, routing congestion has become a critical problem in very large scale integration designs. This paper introduces a distributed metric to predict routing congestion and applies it to technology mapping that targets area and delay optimization. Our technology mapping algorithms are guided by a probabilistic congestion map for the subject graph to identify the congested regions, where congestion-optimal matches are favored. Experimental results on a set of benchmark circuits in a 90-nm technology show that congestion-aware mapping results in a reduction of 37%, on an average, in track overflows with marginal gate-area penalty as compared to conventional area-oriented technology mapping. For delay-oriented mapping, our algorithm improves track overflows by 20%, on an average, in addition to preserving or improving the delay, as compared to the conventional method.