Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A near optimal algorithm for technology mapping minimizing area under delay constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Optimal reliable crosstalk driven interconnect optimization
ICCAD '00 Proceedings of the 2000 international conference on Computer-aided design
Crosstalk noise optimization by post-layout transistor sizing
Proceedings of the 2002 international symposium on Physical design
Crosstalk-Constrained Maze Routing Based on Lagrangian Relaxation
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Pre-Route Noise Estimation in Deep Submicron Integrated Circuits
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Post-Route Gate Sizing for Crosstalk Noise Reduction
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Optimal gate sizing for coupling-noise reduction
Proceedings of the 2004 international symposium on Physical design
Wire length prediction-based technology mapping and fanout optimization
Proceedings of the 2005 international symposium on Physical design
True crosstalk aware incremental placement with noise map
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
IEEE Design & Test
Pattern routing: use and theory for increasing predictability and avoiding coupling
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global and local congestion optimization in technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A predictive distributed congestion metric with application to technology mapping
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Technology mapping algorithm targeting routing congestion under delay constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk-Aware Domino-Logic Synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In today's VLSI designs, crosstalk effects causing chips to fail or suffer from low yields have become one of the very essential design issues. In this paper, we attempt to reduce crosstalk noise in logic and physical synthesis stage, which is usually done in post-layout stage. We propose a technology mapping method that can reduce the crosstalk noise while meeting delay constraints. The algorithm employing a dynamic programming framework in the matching phase determines the routing of fanin nets for all the matches to estimate the track utilization in probability. These routings are stored as virtual routing maps to compute the crosstalk noise during the covering phase, which will select the crosstalk-minimal solutions satisfying the delay constraints rather than the delay-minimal ones. This problem is different from wire congestion-driven technology mapping and our experimental results are encouraging. We experiment on the benchmark circuits in 90nm process, the results show that, with 7% of area increase, our proposed approach is effective to improve the crosstalk by 28% on average, as compared to the conventional delay- and/or congestion-driven technology mapping. The overall result is better than the efforts done in post-layout stage, and has been validated by modern commercial EDA tools. In addition, this proposed approach can be applied in local technology remapping at post-placement/post-routing and ECO stages as well.