A logical approach to discrete math
A logical approach to discrete math
Crosstalk noise optimization by post-layout transistor sizing
Proceedings of the 2002 international symposium on Physical design
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Post-route gate sizing for crosstalk noise reduction
Proceedings of the 40th annual Design Automation Conference
Gate Sizing to Eliminate Crosstalk Induced Timing Violation
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Timing analysis with crosstalk is a fixpoint on a complete lattice
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Yield driven gate sizing for coupling-noise reduction under uncertainty
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Reliable crosstalk-driven interconnect optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Technology mapping with crosstalk noise avoidance
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
Coupling-noise reduction has emerged as a critical design problem with VLSI feature sizes shrinking rapidly and with the use of more aggressive and less noise-immune circuits. Since coupling-noise on a net depends on driving gate-sizes of the net itself and all nets coupled to it, gate-sizing emerges as an effective approach to coupling-noise reduction. It is an attractive approach since re-routing is not required. In this paper, we propose an iterative gate-sizing algorithm to determine optimal gate-sizes for coupling-noise reduction. We consider gate-sizing as a fixpoint computation on a complete lattice and the beauty of the iterative gate-sizing algorithm lies in its ability to guarantee the optimal solution, provided it exists. The effectiveness of the algorithm is validated experimentally by simulations on multiple large circuits.