Post global routing crosstalk risk estimation and reduction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Buffer insertion for noise and delay optimization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Global routing with crosstalk constraints
DAC '98 Proceedings of the 35th annual Design Automation Conference
Application-specific integrated circuits
Application-specific integrated circuits
Crosstalk minimization using wire perturbations
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On switch factor based analysis of coupled RC interconnects
Proceedings of the 37th Annual Design Automation Conference
ClariNet: a noise analysis tool for deep submicron design
Proceedings of the 37th Annual Design Automation Conference
TACO: timing analysis with coupling
Proceedings of the 37th Annual Design Automation Conference
Post-layout transistor sizing for power reduction in cell-based design
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Miller factor for gate-level coupling delay calculation
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Modeling Crosstalk in Resistive VLSI Interconnections
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Crosstalk Noise Estimation for Generic RC Trees
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Gate Sizing to Eliminate Crosstalk Induced Timing Violation
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Signal integrity management in an SoC physical design flow
Proceedings of the 2003 international symposium on Physical design
Post-route gate sizing for crosstalk noise reduction
Proceedings of the 40th annual Design Automation Conference
Optimal gate sizing for coupling-noise reduction
Proceedings of the 2004 international symposium on Physical design
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Yield driven gate sizing for coupling-noise reduction under uncertainty
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Reliable crosstalk-driven interconnect optimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
IEEE Transactions on Computers
Technology mapping with crosstalk noise avoidance
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
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This paper proposes a post-layout transistor sizing method for crosstalk noise reduction. The proposed method downsizes the drivers of the aggressor wires for noise reduction, utilizing the precise interconnect information extracted from the detail-routed layouts. We develop a transistor sizing algorithm for crosstalk noise reduction under delay constraints, and construct a crosstalk noise optimization method utilizing a crosstalk noise estimation method and a transistor sizing framework which are previously developed. Our method exploits the transistor sizing framework that can vary the transistor widths inside cells with interconnects unchanged. Our optimization method therefore never cause a new crosstalk noise problem, and does not need iterative layout optimization. The effectiveness of the proposed method is experimentally examined using 2 circuits. The maximum noise voltage is reduced by more than 50% without delay increase. These results show that the risk of crosstalk noise problems can be considerably reduced after detail-routing.