Aggressor alignment for worst-case coupling noise
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Crosstalk noise optimization by post-layout transistor sizing
Proceedings of the 2002 international symposium on Physical design
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Efficient Delay Calculation in Presence of Crosstalk
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
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We address the problem of crosstalk computation and reduction using circuit and layout techniques in this paper. We provide easily computable expressions for crosstalk amplitude and pulse width in resistive, capacitively coupled lines. The expressions hold for nets with arbitrary number of pins and arbitrary topology. Experimental results show that the average error is about 10% and the maximum error is less than 20%. The expressions are used to motivate circuit techniques such as transistor sizing, and layout techniques such as wire ordering and wire width optimization to reduce crosstalk.