Simultaneous driver and wire sizing for performance and power optimization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Getting to the bottom of deep submicron
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Algorithms, games, and the internet
STOC '01 Proceedings of the thirty-third annual ACM symposium on Theory of computing
Closed form solutions to simultaneous buffer insertion/sizing and wire sizing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Crosstalk noise optimization by post-layout transistor sizing
Proceedings of the 2002 international symposium on Physical design
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Post-Route Gate Sizing for Crosstalk Noise Reduction
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Gate Sizing to Eliminate Crosstalk Induced Timing Violation
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Gate Sizing and Buffer Insertion using Economic Models for Power Optimization
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Timing modeling and optimization under the transmission line model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
In this paper, we develop a new post-layout gate sizing algorithm for simultaneous optimization of interconnect delay and crosstalk noise. We have modeled the problem of gate sizing as a normal form game and solved using the Nash equilibrium. The noise induced on a net depends on the size of the gates driving the coupled nets and itself. Increasing the gate size of the driver increases the noise induced by the net on its coupled nets, where as, increasing the size of the driver of coupled nets increases the noise induced on the net itself, resulting in a conflicting situation. The problem of post-layout gate size optimization is difficult to solve due to its conflicting nature [15]. Game theory provides a natural framework for handling such conflicting situations and allows multi-metric optimization. We have exploited this property of game theory to solve the cyclic dependency of crosstalk noise on its gate sizes, while modeling the problem of gate sizing for simultaneous optimization of interconnect delay and crosstalk noise, which again are conflicting in nature. Experimental results on several medium and large opencore designs indicate average improvements of 13.33% and 16.61% for interconnect delay and crosstalk noise, without any area overhead or need for re-routing.