An efficient surface-based low-power buffer insertion algorithm
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In this paper, we propose new algorithms for gatesizing and buffer insertion that aim at reducing the switchedcapacitance in gate level circuits. We have formulated the gatesizing and the buffer insertion problems as competitive resourceallocation based auction theoretic games and develop solutionsbased on the Nash equilibrium function. The main contributionof this work is in the application of economic models andgame theoretic solutions to logic synthesis problems for poweroptimization. The gate sizing problem is modeled as a ProgressiveSecond Price (PSP) auction, where the players of the auction(representing the gates) bid for partial delays in each path ofthe circuit. The PSP auction process attempts to optimize thepower consumption of each path in the circuit. The bids suppliedby the players are used to determine the allocation for eachplayer in the auction, using a game theoretic formulation. Thesize of a gate is determined based on its delay allocation. The gatesizing problem can be integrated with buffer insertion for betterpower optimization and we develop a game theoretic algorithmfor combined gate sizing and buffer insertion. Experimentalresults on MCNC '91 benchmark circuits indicate that theproposed algorithms provide better power optimization thansimilar approaches in the literature, and are comparable in termsof run times.