Post-Route Gate Sizing for Crosstalk Noise Reduction

Authors:
Murat R. Becer;David Blaauw;Ilan Algor;Rajendran Panda;Chanhee Oh;Vladimir Zolotov;Ibrahim N. Hajj
Affiliations:
-;-;-;-;-;-;-
Venue:
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Year:
2003

Citing 0
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Abstract

Gate sizing is a practical and a feasible crosstalk noisecorrection technique in the post route design stage, especiallyfor block level sea-of-gates designs. The difficulty ingate sizing for noise reduction is that by increasing a driversize, noise at the driver output is reduced, but noise injectedby that driver on other nets is increased. This can createcyclical dependencies between nets in the circuit with noiseviolations. In this paper, we propose a fast and effectiveheuristic post-route gate sizing algorithm that uses a graphrepresentation of the noise dependencies between nodes. Ourmethod utilizes gate sizing in both directions and works inlinear time as a function of the number of gates. The effectivenessof the algorithm is shown on several high performancedesigns.