Introduction to algorithms
Network flows: theory, algorithms, and applications
Network flows: theory, algorithms, and applications
Minimum crosstalk switchbox routing
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Techniques for crosstalk avoidance in the physical design of high-performance digital systems
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Post global routing crosstalk risk estimation and reduction
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
An optimal algorithm for river routing with crosstalk constraints
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Minimum crosstalk channel routing
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A spacing algorithm for performance enhancement and cross-talk reduction
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A new algorithm for floorplan design
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Post-routing timing optimization with routing characterization
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Crosstalk constrained global route embedding
ISPD '99 Proceedings of the 1999 international symposium on Physical design
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Reducing cross-coupling among interconnect wires in deep-submicron datapath design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Pseudo pin assignment with crosstalk noise control
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Domino logic synthesis minimizing crosstalk
Proceedings of the 37th Annual Design Automation Conference
Self-test methodology for at-speed test of crosstalk in chip interconnects
Proceedings of the 37th Annual Design Automation Conference
Fault modeling and simulation for crosstalk in system-on-chip interconnects
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Testing for interconnect crosstalk defects using on-chip embedded processor cores
Proceedings of the 38th annual Design Automation Conference
Early probabilistic noise estimation for capacitively coupled interconnects
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Shield count minimization in congested regions
Proceedings of the 2002 international symposium on Physical design
Crosstalk noise optimization by post-layout transistor sizing
Proceedings of the 2002 international symposium on Physical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Proceedings of the 39th annual Design Automation Conference
False-noise analysis using logic implications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Journal of Electronic Testing: Theory and Applications
Signal integrity management in an SoC physical design flow
Proceedings of the 2003 international symposium on Physical design
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
Journal of Electronic Testing: Theory and Applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Closed-Form Crosstalk Noise Delay Metrics
Analog Integrated Circuits and Signal Processing
A Global Driver Sizing Tool for Functional Crosstalk Noise Avoidance
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Driver modeling and alignment for worst-case delay noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Full-Chip Multilevel Routing for Power and Signal Integrity
Proceedings of the conference on Design, automation and test in Europe - Volume 2
An ECO algorithm for eliminating crosstalk violations
Proceedings of the 2004 international symposium on Physical design
A Fast Crosstalk- and Performance-Driven Multilevel Routing System
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Enhancing Signal Integrity through a Low-Overhead Encoding Scheme on Address Buses
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crosstalk-aware routing resource assignment
Journal of Computer Science and Technology
Dummy fill density analysis with coupling constraints
Proceedings of the 2007 international symposium on Physical design
Power optimal MTCMOS repeater insertion for global buses
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Timing-driven row-based power gating
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2008 international symposium on Physical design
Multi-layer global routing considering via and wire capacities
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip
Microelectronics Journal
Multilayer global routing with via and wire capacity considerations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Technology mapping with crosstalk noise avoidance
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Crosstalk noise reduction in synthesized digital logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On pioneering nanometer-era routing problems
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
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Due to the scaling down of device geometry and increasing frequency in deep sub-micron designs, crosstalk between interconnection wires has become an important issue in VLSI layout design. In this paper, we consider crosstalk avoidance during global routing. W e present a global routing algorithm based on a new Steiner tree formulation and the Lagrangian relaxation technique. W e also give theoretical results on the complexity of the problem.