Multilayer global routing with via and wire capacity considerations

Authors:
Chin-Hsiung Hsu;Huang-Yu Chen;Yao-Wen Chang
Affiliations:
Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan;Design and Technology Platform, Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, Taiwan;Graduate Institute of Electronics Engineering and the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2010

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Abstract

Global routing for modern large-scale circuit designs has attracted much attention in the recent literature. Most of the state-of-the-art academic global routers just work on a simplified routing congestion model that ignores the essential via capacity for routing through multiple metal layers. Such a simplified model would easily cause fatal routability problems in subsequent detailed routing. To remedy this deficiency, a more effective congestion metric that considers both the in-tile nets and the residual via capacity for global routing is presented. Experimental results show that our global router can achieve very high-quality routing solutions with more reasonable via usage.