BoxRouter 2.0: architecture and implementation of a hybrid and robust global router

Authors:
Minsik Cho;Katrina Lu;Kun Yuan;David Z. Pan
Affiliations:
The University of Texas at Austin, Austin, TX;The University of Texas at Austin, Austin, TX;The University of Texas at Austin, Austin, TX;The University of Texas at Austin, Austin, TX
Venue:
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Year:
2007

Citing 26
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PathFinder: a negotiation-based performance-driven router for FPGAs

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Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution

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Congestion aware layout driven logic synthesis

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Pattern routing: use and theory for increasing predictability and avoiding coupling

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Abstract

In this paper, we present BoxRouter 2.0, a hybrid and robust global router with discussion on its architecture and implementation. As high performance VLSI design becomes more interconnect-dominant, efficient congestion elimination in global routing is in greater demand. Hence, we propose BoxRouter 2.0 which has strong ability to improve routability and minimize the number of vias with blockages, while minimizing wirelength. BoxRouter 2.0 is improved over [1], but can perform multi-layer routing with 2D global routing and layer assignment. Our 2D global routing is equipped with two ideas: robust negotiation-based A* search for routing stability, and topology-aware wire ripup for flexibility. After 2D global routing, 2D-to-3D mapping is done by the layer assignment which is powered by progressive via/blockage-aware integer linear programming. Experimental results show that BoxRouter 2.0 has better routability with comparable wirelength than other routers on ISPD07 benchmark, and it can complete (no overflow) ISPD98 benchmark for the first time in the literature with the shortest wirelength.