PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Parallel hierarchical global routing for general cell layout
GLSVLSI '95 Proceedings of the Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
A DFM aware, space based router
Proceedings of the 2007 international symposium on Physical design
Archer: a history-driven global routing algorithm
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
The coming of age of (academic) global routing
Proceedings of the 2008 international symposium on Physical design
Larrabee: a many-core x86 architecture for visual computing
ACM SIGGRAPH 2008 papers
Towards acceleration of fault simulation using graphics processing units
Proceedings of the 45th annual Design Automation Conference
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Accelerating statistical static timing analysis using graphics processing units
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
FastRoute 4.0: global router with efficient via minimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
High-performance global routing with fast overflow reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
GRIP: scalable 3D global routing using integer programming
Proceedings of the 46th Annual Design Automation Conference
Introduction to GPU programming for EDA
Proceedings of the 2009 International Conference on Computer-Aided Design
Going with the flow: bridging the gap between theory and practice in physical design
Proceedings of the 19th international symposium on Physical design
Design planning trends and challenges
Proceedings of the 19th international symposium on Physical design
What makes a design difficult to route
Proceedings of the 19th international symposium on Physical design
Accelerating large graph algorithms on the GPU using CUDA
HiPC'07 Proceedings of the 14th international conference on High performance computing
An effective GPU implementation of breadth-first search
Proceedings of the 47th Design Automation Conference
A parallel integer programming approach to global routing
Proceedings of the 47th Design Automation Conference
Multi-threaded collision-aware global routing with bounded-length maze routing
Proceedings of the 47th Design Automation Conference
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
MaizeRouter: Engineering an Effective Global Router
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing
Proceedings of the International Conference on Computer-Aided Design
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With aggressive technology scaling, the complexity of the global routing problem is poised to rapidly grow. Solving such a large computational problem demands a high throughput hardware platform such as modern Graphics Processing Units (GPU). In this work, we explore a hybrid GPU-CPU high-throughput computing environment as a scalable alternative to the traditional CPU-based router. We introduce Net Level Concurrency (NLC): a novel parallel model for router algorithms that aims to exploit concurrency at the level of individual nets. To efficiently uncover NLC, we design a Scheduler to create groups of nets that can be routed in parallel. At its core, our Scheduler employs a novel algorithm to dynamically analyze data dependencies between multiple nets. We believe such an algorithm can lay the foundation for uncovering data-level parallelism in routing: a necessary requirement for employing high throughput hardware. Detailed simulation results show an average of 4X speedup over NTHU-Route 2.0 with negligible loss in solution quality. To the best of our knowledge, this is the first work on utilizing GPUs for global routing.