Parallel hierarchical global routing for general cell layout

  • Authors:
  • S. Khanna;S. Gao;K. Thulasiraman

  • Affiliations:
  • -;-;-

  • Venue:
  • GLSVLSI '95 Proceedings of the Fifth Great Lakes Symposium on VLSI (GLSVLSI'95)
  • Year:
  • 1995

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Abstract

In this paper we present a parallel global routing algorithm for general cell layout. The algorithm applies a hierarchical decomposition strategy that recursively divides routing problems into simple, independent subproblems for parallel processing. The solution of each subproblem is based on integer programming and network flow optimization. The algorithm is implemented on a shared-memory machine and experiment results on different examples show relative speedup between 4 and 5 for 8 processors. The speedup is achieved without compromising the quality of the routing results.