Topics in parallel integer optimization
Topics in parallel integer optimization
High-performance routing at the nanometer scale
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
BoxRouter 2.0: architecture and implementation of a hybrid and robust global router
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
FastRoute 4.0: global router with efficient via minimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
High-performance global routing with fast overflow reduction
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Computational Experience with a Software Framework for Parallel Integer Programming
INFORMS Journal on Computing
GRIP: scalable 3D global routing using integer programming
Proceedings of the 46th Annual Design Automation Conference
FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An enhanced global router with consideration of general layer directives
Proceedings of the 2011 international symposium on Physical design
The ISPD-2011 routability-driven placement contest and benchmark suite
Proceedings of the 2011 international symposium on Physical design
A SimPLR method for routability-driven placement
Proceedings of the International Conference on Computer-Aided Design
Congestion analysis for global routing via integer programming
Proceedings of the International Conference on Computer-Aided Design
High-quality global routing for multiple dynamic supply voltage designs
Proceedings of the International Conference on Computer-Aided Design
Exploring high throughput computing paradigm for global routing
Proceedings of the International Conference on Computer-Aided Design
Mixed integer programming models for detailed placement
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Confidentiality preserving integer programming for global routing
Proceedings of the 49th Annual Design Automation Conference
GLARE: global and local wiring aware routability evaluation
Proceedings of the 49th Annual Design Automation Conference
The DAC 2012 routability-driven placement contest and benchmark suite
Proceedings of the 49th Annual Design Automation Conference
Proceedings of the International Conference on Computer-Aided Design
ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite
Proceedings of the International Conference on Computer-Aided Design
A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing
Proceedings of the International Conference on Computer-Aided Design
Power-driven global routing for multisupply voltage domains
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
Fast and scalable parallel layout decomposition in double patterning lithography
Integration, the VLSI Journal
Techniques for scalable and effective routability evaluation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We propose a parallel global routing algorithm that concurrently processes routing subproblems corresponding to rectangular subregions covering the chip area. The algorithm uses at it core an existing integer programming (IP) formulation---both for routing each subproblem and for connecting them. Concurrent processing of the routing subproblems is desirable for effective parallelization. However, achieving no (or low) overflow global routing solutions without strong, coordinated algorithmic control is difficult. Our algorithm addresses this challenge via a patching phase that uses IP to connect partial routing solutions. Patching provides feedback to each routing subproblem in order to avoid overflow, later when attempting to connect them. The end result is a flexible and highly scalable distributed algorithm for global routing. The method is able to accept as input target runtimes for its various phases and produce high-quality solution within these limits. Computational results show that for a target runtime of 75 minutes, running on a computational grid of few hundred CPUs with 2GB memory, the algorithm generates higher quality solutions than competing methods in the open literature.