Branch-And-Price: Column Generation for Solving Huge Integer Programs
Operations Research
Post-placement voltage island generation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
FastRoute 2.0: A High-quality and Efficient Global Router
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Logic and Layout Aware Voltage Island Generation for Low Power Design
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
NTHU-Route 2.0: a fast and stable global router
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
GRIP: scalable 3D global routing using integer programming
Proceedings of the 46th Annual Design Automation Conference
Impact of local interconnects on timing and power in a high performance microprocessor
Proceedings of the 19th international symposium on Physical design
A parallel integer programming approach to global routing
Proceedings of the 47th Design Automation Conference
A pareto-algebraic framework for signal power optimization in global routing
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
High-quality global routing for multiple dynamic supply voltage designs
Proceedings of the International Conference on Computer-Aided Design
High-Performance Routing at the Nanometer Scale
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This work presents a method for global routing (GR) to minimize power associated with global nets. We consider routing in designs with multiple supply voltages. Level converters are added to nets that connect driver cells to sink cells of higher supply voltage and are modeled as additional terminals of the nets during GR. Given an initial GR solution obtained with the objective of minimizing wirelength, we propose a GR method to detour nets to further save the power of global nets. When detouring routes via this procedure, overflow is not increased, and the increase in wirelength is bounded. The power saving opportunities include (1) reducing the area capacitance of the routes by detouring fromthe highermetal layers to the lower ones, (2) reducing the coupling capacitance between adjacent routes by distributing the congestion, and (3) considering different power weights for each segment of a routed net with level converters (to capture its corresponding supply voltage and activity factor). We present a mathematical formulation to capture these power saving opportunities and solve it using integer programming techniques. In our simulations, we show considerable saving in a power metric for GR, without any wirelength degradation.