Logic and Layout Aware Voltage Island Generation for Low Power Design

Authors:
Liangpeng Guo;Yici Cai;Qiang Zhou;Xianlong Hong
Affiliations:
EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China;EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China;EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China;EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, China
Venue:
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Year:
2007

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Abstract

Multiple supply voltage (MSV) is one of the most effective schemes to achieve low power, but most works are based on logic level. A few recent works are based on physical level but all of them do not consider level converters which have an important effect in dual-vdd design. In this work we propose a logic and layout aware approach for voltage assignment and voltage island generation in placement process to minimize the number of level converters and to implement voltage islands with minimal overheads. Experimental results show that our approach uses much less level converters than the approach in [1] (reduced by 59.50% on average) when achieving the same power savings. The approach is able to produce feasible placement with a small impact to traditional placement goals.