Activity-driven clock design for low power circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Proceedings of the 6th international workshop on Hardware/software codesign
System-level power estimation and optimization
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Design Challenges of Technology Scaling
IEEE Micro
Subthreshold leakage modeling and reduction techniques
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
State-based power analysis for systems-on-chip
Proceedings of the 40th annual Design Automation Conference
Networks on Silicon: Blessing or Nightmare?
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies
Proceedings of the 2003 international symposium on Low power electronics and design
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Dynamic voltage and frequency scaling based on workload decomposition
Proceedings of the 2004 international symposium on Low power electronics and design
Architecting voltage islands in core-based system-on-a-chip designs
Proceedings of the 2004 international symposium on Low power electronics and design
Balancing hardware intensity in microprocessor pipelines
IBM Journal of Research and Development
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Temperature-Aware Voltage Islands Architecting in System-on-Chip Design
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Power Reduction Technique Using Multi-vt Libraries
IWSOC '05 Proceedings of the Fifth International Workshop on System-on-Chip for Real-Time Applications
TAPHS: thermal-aware unified physical-level and high-level synthesis
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Post-placement voltage island generation under performance requirement
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Timing-constrained and voltage-island-aware voltage assignment
Proceedings of the 43rd annual Design Automation Conference
Voltage island aware floorplanning for power and timing optimization
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Power Delivery Aware Floorplanning for Voltage Island Designs
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Improving voltage assignment by outlier detection and incremental placement
Proceedings of the 44th annual Design Automation Conference
A provably good approximation algorithm for power optimization using multiple supply voltages
Proceedings of the 44th annual Design Automation Conference
Logic and Layout Aware Voltage Island Generation for Low Power Design
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Voltage Island Generation under Performance Requirement for SoC Designs
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Application-driven floorplan-aware voltage island design
Proceedings of the 45th annual Design Automation Conference
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
A thermal aware floorplanning algorithm supporting voltage islands for low power SOC design
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Cell-level placement for improving substrate thermal distribution
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimality and scalability study of existing placement algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generalized Power-Delay Metrics in Deep Submicron CMOS Designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2010 ACM Symposium on Applied Computing
A revisit to voltage partitioning problem
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Energy efficient mapping and voltage islanding for regular NoC under design constraints
International Journal of High Performance Systems Architecture
Energy-efficient scheduling of real-time periodic tasks in multicore systems
NPC'10 Proceedings of the 2010 IFIP international conference on Network and parallel computing
Practically scalable floorplanning with voltage island generation
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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Among the different methods of reducing power for core-based system-on-chip (SoC) designs, the voltage-island technique has gained in popularity. Assigning cores to the different supply voltages and floorplanning to create contiguous voltage islands are two important steps in the design process. We propose a new application-driven approach to voltage partitioning and island creation with the objective of reducing overall SoC power, area, and floorplanner runtime. Given an application power-state machine (PSM), we first identify the suitable range of supply voltages for each core. Then, we generate the discrete voltage assignment table using a heuristic technique. Next, we describe a methodology of reducing the large number of available choices from the voltage assignment table down to a useful set using the application PSM. We partition the cores into islands, using a cost function that gradually shifts from a power-based assignment to a connectivity-based one. Compared with previously reported techniques, a 9.4% reduction in power and 8.7% reduction in area are achieved using our approach, with an average runtime improvement of 2.4 times.