Application-driven voltage-island partitioning for low-power system-on-chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Triple-threshold static power minimization in high-level synthesis of VLSI CMOS
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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In DSM technology leakage power dissipation in a cell becomes significant. Due to this significant rise in leakage power some measures should be taken quite early in the design flow to reduce it rather than realizing it later and either increasing the time to market by increasing the number of iterations or increasing the cost of production by using costly packaging. We have explored various ways of reducing leakage power in the design and recommended one, the Multi-Vt approach. We have carried out analysis using Multi-Vt approach over a test design on 130nm and 90nm technology. We have also highlighted on ways of how and where to apply this approach effectively in a typical ASIC design flow. We compare our results with all other approaches and demonstrate an average reduction in leakage power by almost 4.9 times compared to normal approaches without paying any penalty for speed or even area.