A thermal aware floorplanning algorithm supporting voltage islands for low power SOC design

Authors:
Yici Cai;Bin Liu;Qiang Zhou;Xianlong Hong
Affiliations:
EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, P.R. China;EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, P.R. China;EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, P.R. China;EDA Lab, Department of Computer Science and Technology, Tsinghua University, Beijing, P.R. China
Venue:
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Year:
2005

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Abstract

This paper presents a new floorplanning algorithm emphasizing power reduction for SOC designs using voltage islands. In this algorithm, the supply voltages and positions of blocks are determined simultaneously for both dynamic and static power reduction. Special notice is taken of the interdependence between power and temperature, and thus a block level power and thermal analyzer is incorporated for thermal aware power estimation. Other goals, including area, wire length, as well as level converters and temperature distribution are taken into account, leading to a multi-objective optimization problem, solved using simulated annealing. Experimental results on a set of modified MCNC benchmarks show that introducing voltage islands can reduce the total power by 15% to 30%, and thermal aware voltage island optimization can further reduce the total power by 4% to 15%, as well as promoting even temperature distribution.