A study of tighter lower bounds in LP relaxation based placement
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Seeing the forest and the trees: Steiner wirelength optimization in placemen
Proceedings of the 2006 international symposium on Physical design
A novel net-degree distribution model and its application to floorplanning benchmark generation
Integration, the VLSI Journal
Placement of 3D ICs with thermal and interlayer via considerations
Proceedings of the 44th annual Design Automation Conference
Application-driven floorplan-aware voltage island design
Proceedings of the 45th annual Design Automation Conference
A power-aware algorithm for the design of reconfigurable hardware during high level placement
International Journal of Knowledge-based and Intelligent Engineering Systems - Adaptive Hardwarel / Evolvable Hardware
Using circuit structural analysis techniques for networks in systems biology
Proceedings of the 11th international workshop on System level interconnect prediction
Application-driven voltage-island partitioning for low-power system-on-chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Quantifying academic placer performance on custom designs
Proceedings of the 2011 international symposium on Physical design
Mixed integer programming models for detailed placement
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Artificial bee colony for the standard cell placement problem
International Journal of Metaheuristics
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Placement is an important step in the overall IC design process in deep submicron technologies, as it defines the on-chip interconnects which have become the bottleneck in determining circuit performance. The rapidly increasing design complexity, combined with the demand for the capability of handling nearly flattened designs for physical hierarchy generation, poses significant challenges to existing placement algorithms. There are very few studies dedicated to understanding the optimality (i.e., the comparison of the solution of an algorithm to the optimal solution) and scalability (i.e., the analysis of the degradation of the performance of an algorithm as the input size of the problem increases) of placement algorithms, due to the limited sizes of existing benchmarks and limited knowledge of optimal solutions. The contribution of this work includes three parts. 1) We implemented an algorithm [Placement Examples with Known Optimal (PEKO) algorithm] for generating synthetic benchmarks that have known optimal wirelengths and can match any given net degree distribution profile. 2) Using benchmarks of 10 k to 2 M placeable modules with known optimal solutions, we studied the optimality and scalability of four state-of-the-art placers, Dragon (Wang et al., 2000), Capo (Caldwell et al., 2000), mPL (Chan et al., 2000), and mPG (Chang et al., 2002) from academia, and a leading edge industrial placer, QPlace (Cadence 1999) from Cadence. For the first time our study reveals the gap between the results produced by these tools versus true optimal solutions. The wirelengths produced by these tools are 1.59 to 2.40 times the optimal in the worst cases, and are 1.43 to 2.12 times the optimal on average. As for scalability, the average solution quality of each tool deteriorates by an additional 9% to 17% when the problem size increases by a factor of ten. These results indicate significant room for improvement in existing placement algorithms. 3) We studied the impact of nonlocal nets on the quality of the placers by extending the PEKO algorithm (PEKU algorithm) to generate synthetic placement benchmarks with a known upper bound of the optimal wirelength. For these benchmarks, the wirelengths produced by these tools are 1.75 to 2.18 times the wirelength upper bound in the - worst case, and are 1.62 to 2.07 times the wirelength upper bound on average. Moreover, in our study we found that the effectiveness of the algorithms varies for circuits with different characteristics.