Performance-driven placement of cell based IC's
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Relaxation and clustering in a local search framework: application to linear placement
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Mongrel: hybrid techniques for standard cell placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Optimality and scalability study of existing placement algorithms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A tale of two nets: studies of wirelength progression in physical design
Proceedings of the 2006 international workshop on System-level interconnect prediction
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Placement strategies for cell-based designs which use a linear programming (LP) relaxation are widely believed to have certain weaknesses. Among these is the phenomenon that the relaxed placement produced by the LP-solver often has excessive cell overlap; this makes the relaxed solution quite distant from a legal one and raises questions about the value of the relaxed solution. An implication of this phenomenon is that, while the objective function value (HPWL) yielded by the LP is a valid lower bound on the achievable wire-length, it is quite distant from known upper bounds produced by quality placement tools - i.e., the lower bounds appear to be loose. In this paper we experiment with some straightforward generalizations of the basic LP-formulation aimed at tightening the lower bound. We show that this approach has an interesting dual effect: in addition to tightening lower bounds, it also results in a quantifiably better cell distribution than the simpler LP-formulation. Based on this idea, we have developed a placer which employs the Relaxation Based Local Search framework. Experimental results are reported for PEKO and MCNC FPGA benchmarks.