RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Quantified suboptimality of VLSI layout heuristics
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
On wirelength estimations for row-based placement
ISPD '98 Proceedings of the 1998 international symposium on Physical design
P-Complete Approximation Problems
Journal of the ACM (JACM)
Why interconnect prediction doesn't work
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Wire length prediction based clustering and its application in placement
Proceedings of the 40th annual Design Automation Conference
Measurement of Inherent Noise in EDA Tools
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Implementation and extensibility of an analytic placer
Proceedings of the 2004 international symposium on Physical design
Proceedings of the 2004 international symposium on Physical design
Pre-layout wire length and congestion estimation
Proceedings of the 41st annual Design Automation Conference
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Large-Scale Circuit Placement: Gap and Promise
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fast and accurate rectilinear steiner minimal tree algorithm for VLSI design
Proceedings of the 2005 international symposium on Physical design
Evaluation of placer suboptimality via zero-change netlist transformations
Proceedings of the 2005 international symposium on Physical design
Capo: robust and scalable open-source min-cut floorplacer
Proceedings of the 2005 international symposium on Physical design
Recursive bisection placement: feng shui 5.0 implementation details
Proceedings of the 2005 international symposium on Physical design
Dragon2005: large-scale mixed-size placement tool
Proceedings of the 2005 international symposium on Physical design
A study of tighter lower bounds in LP relaxation based placement
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
FLUTE: fast lookup table based wirelength estimation technique
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Optimality and scalability study of existing placement algorithms
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Architecture and details of a high quality, large-scale analytical placer
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Edge separability-based circuit clustering with application to multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast wire length estimation by net bundling for block placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
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At every stage in physical design, engineers are faced with many different objectives and tools to develop, optimize, and evaluate their design. Each choice of a tool or an objective to optimize can potentially lead to a completely different final physically designed circuit. Furthermore, some of the objectives optimized by the tools are not necessarily the best or right objectives, but rather compromised objectives; for example, placers optimize the half-perimeter wirelength rather than the routed wirelength. The contributions of this paper are twofold. First, we define and use a metric to measure the consistency of optimizing wirelength during the different stages of physical design. Our main technique is based on tracing the relative lengths of two nets - or more accurately pairs of nets - as they progress through the physical design flow. Second, we propose a simple method to quantify the similarity between the results of different tools. Our empirical results point out to the physical design stages where vulnerability can occur from optimizing compromised objectives.