Efficient and effective placement for very large circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A timing driven N-way chip and multi-chip partitioner
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Pre-layout estimation of individual wire lengths
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Edge separability based circuit clustering with application to circuit partitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Fine granularity clustering for large scale placement problems
Proceedings of the 2003 international symposium on Physical design
When clusters meet partitions: new density-based methods for circuit decomposition
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
A wire length estimation technique utilizing neighborhood density equations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An evaluation of bipartitioning techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On wirelength estimations for row-based placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Pre-layout wire length and congestion estimation
Proceedings of the 41st annual Design Automation Conference
Individual wire-length prediction with application to timing-driven placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Sequential delay budgeting with interconnect prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire length prediction-based technology mapping and fanout optimization
Proceedings of the 2005 international symposium on Physical design
A congestion-driven placement framework with local congestion prediction
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Pre-layout Physical Connectivity Prediction with Application in Clustering-Based Placement
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Multilevel expansion-based VLSI placement with blockages
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A priori prediction of tightly clustered connections based on heuristic classification trees
Proceedings of the 2006 international workshop on System-level interconnect prediction
A tale of two nets: studies of wirelength progression in physical design
Proceedings of the 2006 international workshop on System-level interconnect prediction
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Timing-aware power noise reduction in layout
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Via-configurable routing architectures and fast design mappability estimation for regular fabrics
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Techniques for effective distributed physical synthesis
Proceedings of the 44th annual Design Automation Conference
Transition-aware decoupling-capacitor allocation in power noise reduction
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A pre-placement net length estimation technique for mixed-size circuits
Proceedings of the 11th international workshop on System level interconnect prediction
Fast, accurate a priori routing delay estimation
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
Layout aware optimization of high speed fixed coefficient FIR filters for FPGAs
International Journal of Reconfigurable Computing
A pre-placement individual net length estimation model and an application for modern circuits
Integration, the VLSI Journal
Designing via-configurable logic blocks for regular fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
| Hi-index | 0.00 |
In this paper we introduce a metric to evaluate proximity of connected elements in a netlist. Compared to connectivity [8] and edge separability [4], our metric is capable of predicting short connections more accurately. We show that the proposed metric can also predict relative wire length in multi-pin nets. We develop a fine-granularity clustering algorithm based on the new metric and embed it into the Fast Placer Implementation (FPI) framework [10]. Experimental results show that the new clustering algorithm produces better global placement results than the net absorption [10] algorithm, connectivity [8], and edge separability [4] based algorithms. With the new clustering algorithm, FPI achieves up to 50% speedup compared to the latest version of Capo8.5 [19], without placement quality losses.