A wire length estimation technique utilizing neighborhood density equations
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Prelayout estimation of individual wire lengths
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Proceedings of the 2003 international workshop on System-level interconnect prediction
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Proceedings of the 2003 international symposium on Physical design
Wire length prediction based clustering and its application in placement
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Pre-layout wire length and congestion estimation
Proceedings of the 41st annual Design Automation Conference
A semi-persistent clustering technique for VLSI circuit placement
Proceedings of the 2005 international symposium on Physical design
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Proceedings of the 2005 international symposium on Physical design
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Proceedings of the 2005 international symposium on Physical design
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Proceedings of the 2006 international symposium on Physical design
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Proceedings of the 2006 international symposium on Physical design
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Proceedings of the 2006 international symposium on Physical design
Intrinsic shortest path length: a new, accurate a priori wirelength estimator
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Tutorial on congestion prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
Fast wire length estimation by net bundling for block placement
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque Blocks
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
A wire length estimation technique utilizing neighborhood density equations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On wirelength estimations for row-based placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Edge separability-based circuit clustering with application to multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A pre-placement individual net length estimation model and an application for modern circuits
Integration, the VLSI Journal
Cut-demand based routing resource allocation and consolidation for routability enhancement
Proceedings of the 16th Asia and South Pacific Design Automation Conference
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An accurate model for pre-placement wire length estimation can be a useful tool during the physical design of integrated circuits. In this paper, an a priori wire length estimation technique for mixed-size circuits is proposed. The proposed technique is capable of predicting the wire lengths for individual nets, and uses both relevant factors used in previous research as well as new factors that can affect the net lengths in mixed-size designs. The proposed model's main characteristics include reporting individual net lengths, suitability for mixed-size designs, and the power to predict pre-placement net lengths before and after clustering. The net lengths estimated by this model are shown to be an average of 10% more correlated to after placement lengths compared to the most elaborated model of literature. The model can be used for a priori individual net length estimation and predicting the possible effects of clustering on lengths of individual nets during the placement stage.