Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
On multilevel circuit partitioning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Improved algorithms for hypergraph bipartitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Fine granularity clustering for large scale placement problems
Proceedings of the 2003 international symposium on Physical design
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
An Effective Multilevel Algorithm for Bisecting Graphs and Hypergraphs
IEEE Transactions on Computers
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
A semi-persistent clustering technique for VLSI circuit placement
Proceedings of the 2005 international symposium on Physical design
The ISPD2005 placement contest and benchmark suite
Proceedings of the 2005 international symposium on Physical design
Capo: robust and scalable open-source min-cut floorplacer
Proceedings of the 2005 international symposium on Physical design
Recursive bisection placement: feng shui 5.0 implementation details
Proceedings of the 2005 international symposium on Physical design
NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs
Proceedings of the 2005 international symposium on Physical design
Engineering details of a stable force-directed placer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Edge separability-based circuit clustering with application to multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An effective clustering algorithm for mixed-size placement
Proceedings of the 2007 international symposium on Physical design
A pre-placement net length estimation technique for mixed-size circuits
Proceedings of the 11th international workshop on System level interconnect prediction
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The complexity and size of digital circuits has grown exponentially and today's circuits can contain millions of logic elements. Clustering algorithms have become popular due to their ability to reduce the circuit sizes so that circuit layout can be performed faster and with higher quality. This paper presents a deterministic, net-reduction based clustering algorithm, called Net Cluster. The basic idea of the proposed technique is to put the emphasis of clustering on reducing the number of nets versus the number of cells. The proposed algorithm has proven linear time complexity of O(p), where p is the number of pins in a circuit. To demonstrate the effectiveness of the proposed clustering technique, it has been applied to multilevel partitioning process. The numerical experiments on ISPD98 benchmark suite demonstrate that by applying Net Cluster, the performance of state-of-the-art multilevel partitioners can be further improved.