Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Improved algorithms for hypergraph bipartitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Fine granularity clustering for large scale placement problems
Proceedings of the 2003 international symposium on Physical design
Optimality, scalability and stability study of partitioning and placement algorithms
Proceedings of the 2003 international symposium on Physical design
A study of netlist structure and placement efficiency
Proceedings of the 2004 international symposium on Physical design
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
A semi-persistent clustering technique for VLSI circuit placement
Proceedings of the 2005 international symposium on Physical design
Capo: robust and scalable open-source min-cut floorplacer
Proceedings of the 2005 international symposium on Physical design
Recursive bisection placement: feng shui 5.0 implementation details
Proceedings of the 2005 international symposium on Physical design
Engineering details of a stable force-directed placer
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Net cluster: a net-reduction based clustering preprocessing algorithm
Proceedings of the 2006 international symposium on Physical design
mPL6: enhanced multilevel mixed-size placement
Proceedings of the 2006 international symposium on Physical design
A faster implementation of APlace
Proceedings of the 2006 international symposium on Physical design
Architecture and details of a high quality, large-scale analytical placer
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Edge separability-based circuit clustering with application to multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast hierarchical quadratic placement algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Force-Directed Methods for Generic Placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A study of routability estimation and clustering in placement
Proceedings of the 2009 International Conference on Computer-Aided Design
SafeChoice: a novel clustering algorithm for wirelength-driven placement
Proceedings of the 19th international symposium on Physical design
A pre-placement individual net length estimation model and an application for modern circuits
Integration, the VLSI Journal
| Hi-index | 0.00 |
Placement is a crucial step for the VLSI circuit physical design and it has a deep impact on the overall circuit performance. Numerous clustering techniques have been proposed and applied to placement to deal with the increasing circuit sizes and complexity. In this paper, an effective clustering algorithm for mixed-size placement is presented. This technique uses local cell connectivity information to identify all potential clusters, but finalizes clusters globally. The effectiveness of the proposed clustering technique is verified by empirical tests on ICCAD04 and ISPD05 benchmark circuits. Specifically, 4 major academic placers, including Capo10.1, FengShui5.1, mPL6 and NTUPlace3-LE, are tested by using the proposed clustering technique as a preprocessing step. The overall experimental results show that for ICCAD04 benchmarks, the proposed clustering technique consistently improves all of the placers' performance by 2% to 5% on average in term of the pin-to-pin half perimeter wire length, with comparable or lower runtime. For ISPD05 benchmarks, the proposed clustering technique shows promising results.