Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Multilevel generalized force-directed method for circuit placement
Proceedings of the 2005 international symposium on Physical design
The ISPD2005 placement contest and benchmark suite
Proceedings of the 2005 international symposium on Physical design
ISPD 2006 Placement Contest: Benchmark Suite and Results
Proceedings of the 2006 international symposium on Physical design
mPL6: enhanced multilevel mixed-size placement
Proceedings of the 2006 international symposium on Physical design
A faster implementation of APlace
Proceedings of the 2006 international symposium on Physical design
An effective clustering algorithm for mixed-size placement
Proceedings of the 2007 international symposium on Physical design
A high-quality mixed-size analytical placer considering preplaced blocks and density constraints
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
RQL: global placement via relaxed quadratic spreading and linearization
Proceedings of the 44th annual Design Automation Conference
FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Edge separability-based circuit clustering with application to multilevel circuit partitioning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fine granularity clustering-based placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Multilevel fixed-point-addition-based VLSI placement
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast hierarchical quadratic placement algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Line search-based inverse lithography technique for mask design
VLSI Design - Special issue on New Algorithmic Techniques for Complex EDA Problems
LatchPlanner: latch placement algorithm for datapath-oriented high-performance VLSI designs
Proceedings of the International Conference on Computer-Aided Design
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This paper presents SafeChoice (SC), a novel clustering algorithm for wirelength-driven placement. Unlike all previous approaches, SC is proposed based on a fundamental theorem, safe condition which guarantees that clustering would not degrade the placement wirelength. To derive such a theorem, we first introduce the concept of safe clustering, i.e., do clustering without degrading the placement quality. To check the safe condition for pair-wise clustering, we propose selective enumeration technique. SC maintains a global priority queue (PQ) based on the safeness and area of potential clusters. Iteratively the cluster at the top of the PQ is formed. SC automatically stops clustering when generating more clusters would degrade the placement wirelength. To achieve other clustering objectives, e.g., any target clustering ratio, SC is able to perform under three different modes. Comprehensive experimental results show that the clusters produced by SC consistently help the placer to achieve the best wirelength among all other clustering algorithms.