Efficient and effective placement for very large circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: application in VLSI domain
DAC '97 Proceedings of the 34th annual Design Automation Conference
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Attractor-repeller approach for global placement
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Consistent placement of macro-blocks using floorplanning and standard-cell placement
Proceedings of the 2002 international symposium on Physical design
Routability driven white space allocation for fixed-die standard-cell placement
Proceedings of the 2002 international symposium on Physical design
FAR: fixed-points addition & relaxation based placement
Proceedings of the 2002 international symposium on Physical design
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
PROUD: A Sea-Of-Gates Placement Algorithm
IEEE Design & Test
Wire length prediction based clustering and its application in placement
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2004 international symposium on Physical design
An Enhanced Multilevel Algorithm for Circuit Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Fractional Cut: Improved Recursive Bisection Placement
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Multilevel vlsi placement in very deep sub-micron technology
Multilevel vlsi placement in very deep sub-micron technology
Optimal partitioners and end-case placers for standard-cell layout
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrated code and data placement in two-dimensional mesh based chip multiprocessors
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
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The rapid growth of system-on-chip designs makes it a necessity for physical design tools to efficiently handle the coexistence of large intellectual property (IP) blocks and small standard cells in a single design. In this work, we present an efficient expansion-based placer to address standard-cell placement problem in the presence of blockages induced by pre-placed IP blocks. Expansion refers to the process during which cells are gradually distributed over a specified region. We implement expansion in a new placer by enhancing a quadratic placement technique based on fixed-point addition originally presented by B. Hu and M. Marek-Sadowska (2003), where fixed points were defined as dimensionless pseudo cells, and were deliberately introduced into the circuit to pull cells from one location to another. The new placer not only produces very competitive placement results over multiple sets of public-domain benchmarks with conventional rectangle-like chip boundary, but also efficiently handles the existence of blockages. Especially, we develop three expansion strategies and use them under different blockage settings.