A min-cut placement algorithm for general cell assemblies based on a graph representation
DAC '79 Proceedings of the 16th Design Automation Conference
An analytic net weighting approach for performance optimization in circuit placement
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Clock routing for high-performance ICs
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
An algorithm for performance-driven initial placement of small-cell ICs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
A fast state assignment procedure for large FSMs
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Algorithms for large-scale flat placement
DAC '97 Proceedings of the 34th annual Design Automation Conference
DAC '97 Proceedings of the 34th annual Design Automation Conference
Partitioning-based standard-cell global placement with an exact objective
Proceedings of the 1997 international symposium on Physical design
Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Unifying behavioral synthesis and physical design
Proceedings of the 37th Annual Design Automation Conference
Algorithms for detailed placement of standard cells
Proceedings of the conference on Design, automation and test in Europe
Multilevel optimization for large-scale circuit placement
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Direct transistor-level layout for digital blocks
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An efficient placement method for large standard-cell and sea-of-gates designs
EURO-DAC '90 Proceedings of the conference on European design automation
MOLE: a sea-of-gates detailed router
EURO-DAC '90 Proceedings of the conference on European design automation
Boosting: Min-Cut Placement with Improved Signal Delay
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Implementation and extensibility of an analytic placer
Proceedings of the 2004 international symposium on Physical design
A study of netlist structure and placement efficiency
Proceedings of the 2004 international symposium on Physical design
Large-scale placement by grid-warping
Proceedings of the 41st annual Design Automation Conference
Large-Scale Circuit Placement: Gap and Promise
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
IEEE Design & Test
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Timing-driven placement by grid-warping
Proceedings of the 42nd annual Design Automation Conference
Physical placement driven by sequential timing analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Multilevel expansion-based VLSI placement with blockages
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Defect tolerance at the end of the roadmap
Nano, quantum and molecular computing
A morphing approach to address placement stability
Proceedings of the 2007 international symposium on Physical design
Geometric quadrisection in linear time, with application to VLSI placement
Discrete Optimization
Proceedings of the International Conference on Computer-Aided Design
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An efficient method is proposed for placing modules in large and highly complex sea-of-gates chips that include preplaced I/O pads and macrocells. PROUD repeatedly solves sparse linear equations. A resistive network analogy of the placement problem and convexity of the objective function are key concepts in this algorithm. The algorithm was tested on nine real circuits. For a triple-metal-layer, 100000-gate sea-of-gate design with 26000 instances, the constructive phase took 50 minutes on a VAX 8650 and yielded excellent results for total wire length. Extensions of the method are considered.