Methods for hierarchical automatic layout of custom LSI circuit masks
DAC '78 Proceedings of the 15th Design Automation Conference
A proper model for the partitioning of electrical circuits
DAC '72 Proceedings of the 9th Design Automation Workshop
The siemens-avesta-system for computer-aided design of MOS-standard cell circuits
DAC '77 Proceedings of the 14th Design Automation Conference
A class of min-cut placement algorithms
DAC '77 Proceedings of the 14th Design Automation Conference
A dynamic and efficient representation of building-block layout
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
VLSI cell placement techniques
ACM Computing Surveys (CSUR)
An analytic net weighting approach for performance optimization in circuit placement
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Branch-and-bound placement for building block layout
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Parallel algorithms for slicing based final placement
EURO-DAC '92 Proceedings of the conference on European design automation
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Partitioning-based standard-cell global placement with an exact objective
Proceedings of the 1997 international symposium on Physical design
Proud: a fast sea-of-gates placement algorithm
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Connectivity biased channel construction and ordering for building-block layout
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Decomposition of logic networks into silicon
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
On the relative placement and the transportation problem for standard-cell layout
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Attractor-repeller approach for global placement
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Some issues raised in physical design workshop 1987
ACM SIGDA Newsletter
PROUD: A Sea-Of-Gates Placement Algorithm
IEEE Design & Test
Automatic component placement in an interactive minicomputer environment
DAC '81 Proceedings of the 18th Design Automation Conference
An automatic/interactive layout planning system for arbitrarily-sized rectangular building blocks
DAC '81 Proceedings of the 18th Design Automation Conference
Automatic placement of rectangular blocks with the interconnection channels
DAC '81 Proceedings of the 18th Design Automation Conference
Placement of variable size circuits on LSI masterslices
DAC '81 Proceedings of the 18th Design Automation Conference
MILD - A cell-based layout system for MOS-LSI
DAC '81 Proceedings of the 18th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
Cell map representation for hierarchical layout
DAC '80 Proceedings of the 17th Design Automation Conference
A data structure for gridless routing
DAC '80 Proceedings of the 17th Design Automation Conference
An analytical method for compacting routing area in integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
The “PI” (placement and interconnect) system
DAC '82 Proceedings of the 19th Design Automation Conference
A placement algorithm for polycell LSI and ITS evaluation
DAC '82 Proceedings of the 19th Design Automation Conference
A combined force and cut algorithm for hierarchical VLSI layout
DAC '82 Proceedings of the 19th Design Automation Conference
Two-dimensional channel routing and channel intersection problems
DAC '82 Proceedings of the 19th Design Automation Conference
Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
Fast Hierarchical Floorplanning with Congestion and Timing Control
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Towards optimizing global MinCut partitioning
EURO-DAC '91 Proceedings of the conference on European design automation
SHARP-looking geometric partitioning
EURO-DAC '91 Proceedings of the conference on European design automation
Floorplanning strategy for mixed analog-digital VLSI integrated circuits
EURO-DAC '91 Proceedings of the conference on European design automation
Goal oriented slicing enumeration through shape function clipping
EURO-DAC '91 Proceedings of the conference on European design automation
A Floorplanning-Synthesis Methodology For Multiple Chip Module Design
Journal of Integrated Design & Process Science
Good Layouts for Pattern Recognizers
IEEE Transactions on Computers
A computer-aided VLSI layout system
AFIPS '81 Proceedings of the May 4-7, 1981, national computer conference
An efficient heuristic for standard-cell placement
Integration, the VLSI Journal
The continuous hopfield networks (CHN) for the placement of the electronic circuits problem
WSEAS Transactions on Computers
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A new placement algorithm for general cell assemblies is presented which combines the ideas of polar graph representation and min-cut placement. First a detailed description of the initial placement procedure is given, then the various methods for placement improvement (rotation, squeezing, reflecting) and global routing are discussed. A sample circuit is used to demonstrate the performance of the algorithms. Results are shown to compare favorably with manually achieved solutions.