Graph Algorithms
An automatic/interactive layout planning system for arbitrarily-sized rectangular building blocks
DAC '81 Proceedings of the 18th Design Automation Conference
Automatic placement of rectangular blocks with the interconnection channels
DAC '81 Proceedings of the 18th Design Automation Conference
SHARPS: A hierarchical layout system for VLSI
DAC '81 Proceedings of the 18th Design Automation Conference
Methods for hierarchical automatic layout of custom LSI circuit masks
DAC '78 Proceedings of the 15th Design Automation Conference
DAC '80 Proceedings of the 17th Design Automation Conference
The genealogical approach to the layout problem
DAC '80 Proceedings of the 17th Design Automation Conference
Cell map representation for hierarchical layout
DAC '80 Proceedings of the 17th Design Automation Conference
Automatic layout of low-cost quick-turnaround random-logic custom LSI devices
DAC '76 Proceedings of the 13th Design Automation Conference
LTX - a system for the directed automatic design of LSI circuits
DAC '76 Proceedings of the 13th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
A min-cut placement algorithm for general cell assemblies based on a graph representation
DAC '79 Proceedings of the 16th Design Automation Conference
A hierarchical placement procedure with a simple blocking scheme
DAC '79 Proceedings of the 16th Design Automation Conference
CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI
DAC '79 Proceedings of the 16th Design Automation Conference
MIRAGE - a simple-model routing program for the hierarchical layout design of IC masks
DAC '79 Proceedings of the 16th Design Automation Conference
Placement and routing algorithms for hierarchical integrated circuit layout
Placement and routing algorithms for hierarchical integrated circuit layout
Linear ordering and application to placement
DAC '83 Proceedings of the 20th Design Automation Conference
A global routing algorithm for general cells
DAC '84 Proceedings of the 21st Design Automation Conference
A symbolic-interconnect router for custom IC design
DAC '84 Proceedings of the 21st Design Automation Conference
Topological routing of multi-bit data buses
DAC '84 Proceedings of the 21st Design Automation Conference
Hi-index | 0.02 |
The automated layout facilities of the ASHLAR program, currently under development at the Defense Systems Division of Sperry Univac, are described. ASHLAR is an interactive layout system to be used in developing hierarchical VLSI designs with cells having arbitrary dimensions. Treatment of the problems of placement, power bus routing, and polysilicon interconnect usage are given particular attention. Finally, some results of a prototype implementation are presented.