Methods for hierarchical automatic layout of custom LSI circuit masks
DAC '78 Proceedings of the 15th Design Automation Conference
DAC '76 Proceedings of the 13th Design Automation Conference
MIRAGE - a simple-model routing program for the hierarchical layout design of IC masks
DAC '79 Proceedings of the 16th Design Automation Conference
Parallel algorithms for slicing based final placement
EURO-DAC '92 Proceedings of the conference on European design automation
TINA: analog placement using enumerative techniques capable of optimizing both area and net length
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
A new area and shape function estimation technique for VLSI layouts
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
HAPPI: a chip compiler based on double-level-metal technology
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Floorplan representations: Complexity and connections
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Placement algorithms for custom VLSI
DAC '83 Proceedings of the 20th Design Automation Conference
Performance of algorithms for initial placement
DAC '84 Proceedings of the 21st Design Automation Conference
Spider, a chip planner for ISL technology
DAC '84 Proceedings of the 21st Design Automation Conference
The planar package planner for system designers
DAC '82 Proceedings of the 19th Design Automation Conference
SAGA: An Experimental Silicon Assembler
DAC '82 Proceedings of the 19th Design Automation Conference
Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
Placement algorithms for custom VLSI
Computer-Aided Design
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The concept of the genealogical approach to the layout problem is presented. The system pursues the idea of flexible modules and is capable of dealing with arbitrarily complex tasks. The genealogical tree of the system provides a mainframe for organizing the information flow. Results of the system routines are described in terms of transitions between flexibility classes of modules.