Introduction to VLSI Systems
The Design and Analysis of Computer Algorithms
The Design and Analysis of Computer Algorithms
Routing method for VLSI design using irregular cells
DAC '83 Proceedings of the 20th Design Automation Conference
A hiererachical, error-tolerant compactor
DAC '84 Proceedings of the 21st Design Automation Conference
A new two-dimensional routing algorithm
DAC '82 Proceedings of the 19th Design Automation Conference
The “PI” (placement and interconnect) system
DAC '82 Proceedings of the 19th Design Automation Conference
Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Wire Ordering for Detailed Routing
IEEE Design & Test
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The router described in this paper is part of a complete CAD system which aims at hierarchical designs of customized VLSI MOS circuits. It routes global signals as symbolic interconnect and is guaranteed to complete all routing in one pass. The router is fully automatic as well as highly interactive. It employs the novel idea of bouyancy and produces wires with a natural bus structure. The router is fully operational, and has been used in routing a number of real-world integrated circuits.