A polynomial algorithm for the min-cut linear arrangement of trees
Journal of the ACM (JACM)
FLOSS: an approach to automated layout for high-volume designs
25 years of DAC Papers on Twenty-five years of electronic design automation
Placement algorithms for arbitrarily shaped blocks
25 years of DAC Papers on Twenty-five years of electronic design automation
Reducing channel density in standard cell layout
DAC '83 Proceedings of the 20th Design Automation Conference
Linear ordering and application to placement
DAC '83 Proceedings of the 20th Design Automation Conference
CELTIC - solving the problems of LSI design with an integrated polycell DA system
DAC '81 Proceedings of the 18th Design Automation Conference
MILD - A cell-based layout system for MOS-LSI
DAC '81 Proceedings of the 18th Design Automation Conference
An Interactive Graphics System for the design of integrated circuits
DAC '78 Proceedings of the 15th Design Automation Conference
Methods for hierarchical automatic layout of custom LSI circuit masks
DAC '78 Proceedings of the 15th Design Automation Conference
Issues in IC implementation of high level, abstract designs
DAC '80 Proceedings of the 17th Design Automation Conference
The Standard Transistor Array (star) (Part II automatic cell placement techniques)
DAC '80 Proceedings of the 17th Design Automation Conference
Floss: An approach to automated layout for high-volume designs
DAC '77 Proceedings of the 14th Design Automation Conference
Automated layout in ASHLAR: An approach to the problems of “General Cell” layout for VLSI
DAC '82 Proceedings of the 19th Design Automation Conference
Optimal layout of CMOS functional arrays
DAC '79 Proceedings of the 16th Design Automation Conference
MIRAGE - a simple-model routing program for the hierarchical layout design of IC masks
DAC '79 Proceedings of the 16th Design Automation Conference
Placement algorithms for arbitrarily shaped blocks
DAC '79 Proceedings of the 16th Design Automation Conference
Optimal Layout of CMOS Functional Arrays
IEEE Transactions on Computers
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This paper discusses the application of the RCA-developed standard cell approach for generating low-cost, quick-turnaround random-logic LSI arrays using automatic placement and routing computer programs. Originally developed with government support1 for two-phase PMOS dynamic logic in 1967, the programs have been expanded to include many technologies2,3 and have gone through extensive evolutionary and revolutionary changes during the past 10 years. They have been used extensively by various government agencies and by many industrial concerns, including RCA. Perhaps a 1000 arrays using the PMOS, CMOS, and CMOS-SOS technologies have been generated using these programs and their derivations in the various companies. Within RCA more than 200 LSI arrays have been generated by these technologies. This paper describes these techniques and discusses various LSI circuits that demonstrate the operation of these programs, as well as the major changes that have occurred in them during the past 10 years. The applications include large LSI systems in addition to individual LSI circuit applications. The Multiport Placement and Routing Algorithm, which is introduced for the first time, demonstrates several CMOS-SOS LSI circuits (including the fastest and most powerful microprocessor yet designed) which show densities comparable to handcrafted custom LSI chips.