The standard transistor array (STAR): Part I A two-layer metal semicustom design system
DAC '80 Proceedings of the 17th Design Automation Conference
Automatic layout of low-cost quick-turnaround random-logic custom LSI devices
DAC '76 Proceedings of the 13th Design Automation Conference
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
Automated cell placement techniques for the standard transistor array (star).
Automated cell placement techniques for the standard transistor array (star).
Optimal folding of standard and custom cells
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automatic placement a review of current techniques (tutorial session)
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
The standard transistor array (STAR): Part I A two-layer metal semicustom design system
DAC '80 Proceedings of the 17th Design Automation Conference
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Layout of a STAR device consists of the placement of standard cells (circuit elements) on the array and the routing of conductors between cells. Cell placement must be such that routing is not hindered. Also, placement procedures must be cost effective and easy to implement on a digital computer. A placement procedure for STARs is described in this paper that satisfies these characteristics. The procedure attempts to optimize the placement with respect to several criteria including expected routing channel usage and routing VIA requirements. Computer implementations of the procedure are discussed. Experimental results are presented which indicate that the procedure yields near-optimum results in computationally convenient amounts of time.