Automatic layout of low-cost quick-turnaround random-logic custom LSI devices
DAC '76 Proceedings of the 13th Design Automation Conference
LTX - a system for the directed automatic design of LSI circuits
DAC '76 Proceedings of the 13th Design Automation Conference
Clustering and linear placement
DAC '72 Proceedings of the 9th Design Automation Workshop
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
IC mask layout with a single conductor layer
DAC '70 Proceedings of the 7th Design Automation Workshop
An algorithm for automatic line routing on Schematic Drawings
DAC '75 Proceedings of the 12th Design Automation Conference
An integrated CAD data base system
DAC '75 Proceedings of the 12th Design Automation Conference
An artwork design verification system
DAC '75 Proceedings of the 12th Design Automation Conference
Improved compaction by minimized length of wires
DAC '83 Proceedings of the 20th Design Automation Conference
Experiments with the SLIM Circuit Compactor
DAC '83 Proceedings of the 20th Design Automation Conference
Interactive compaction router for VLSI layout
DAC '84 Proceedings of the 21st Design Automation Conference
The evolution of design automation to meet the challanges of VLSI
DAC '80 Proceedings of the 17th Design Automation Conference
The VLSI design challenge of the 80's (Position Statement)
DAC '80 Proceedings of the 17th Design Automation Conference
A symbolic design system for integrated circuits
DAC '82 Proceedings of the 19th Design Automation Conference
CALMOS: A portable software system for the automatic and interactive layout of MOS/LSI
DAC '79 Proceedings of the 16th Design Automation Conference
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Traditionally, automatic IC layout programs have been constrained to produced designs in which cells are placed in rows. The resulting chips are typically too large, compared to manual layout, to be used for high-volume production. FLOSS uses a new approach &emdash; automatic packing of a manually-generated sketch &emdash; to achieve chip area that is competitive with manual layout.