A dynamic and efficient representation of building-block layout
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
A new compaction scheme based on compression ridges
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
FLOSS: an approach to automated layout for high-volume designs
25 years of DAC Papers on Twenty-five years of electronic design automation
SLIM - The translation of symbolic layouts into mask data
25 years of DAC Papers on Twenty-five years of electronic design automation
25 years of DAC Papers on Twenty-five years of electronic design automation
Symbolic layout compaction review
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Two-dimensional compaction by “zone refining”
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
ACM SIGDA Newsletter
Comparative router performance
ACM SIGDA Newsletter
Experiments with the SLIM Circuit Compactor
DAC '83 Proceedings of the 20th Design Automation Conference
Interactive compaction router for VLSI layout
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
SLIM-the translation of symbolic layouts into mask data
DAC '80 Proceedings of the 17th Design Automation Conference
The node cost measure for embedding graphs on the planar grid (Extended Abstract)
STOC '80 Proceedings of the twelfth annual ACM symposium on Theory of computing
On the topological aspects of the circuit layout problem
DAC '76 Proceedings of the 13th Design Automation Conference
Floss: An approach to automated layout for high-volume designs
DAC '77 Proceedings of the 14th Design Automation Conference
An improved graph-theoretic model for the circuit layout problem
DAC '74 Proceedings of the 11th Design Automation Workshop
On old and new routing problems
Proceedings of the 2011 international symposium on Physical design
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A computer program for the automatic layout of single conductor layer IC masks is described. Descriptions are included of element modelling, element placement, grid expansion, cross-over minimization, conductor routing and layout compaction.