Information transfer and area-time tradeoffs for VLSI multiplication
Communications of the ACM
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
SLIM-the translation of symbolic layouts into mask data
DAC '80 Proceedings of the 17th Design Automation Conference
IC mask layout with a single conductor layer
DAC '70 Proceedings of the 7th Design Automation Workshop
Optimal wiring between rectangles
STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
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The two major cost measures used in the past for grid embeddings are area (or the area of the smallest square or rectangle that contains the embedding) and total edge length. This paper is primarily concerned with a third measure, total number of nodes. To embed a graph on the planar grid, it may be necessary to “bend” edges. This can be modeled by allowing the insertion of nodes along edges of the graph and then insisting that the embedding may not bend edges.