Introduction to VLSI Systems
An optimal solution to a wire-routing problem (preliminary version)
STOC '80 Proceedings of the twelfth annual ACM symposium on Theory of computing
Optimal tree layout (Preliminary Version)
STOC '80 Proceedings of the twelfth annual ACM symposium on Theory of computing
The node cost measure for embedding graphs on the planar grid (Extended Abstract)
STOC '80 Proceedings of the twelfth annual ACM symposium on Theory of computing
Bristle Blocks: A silicon compiler
DAC '79 Proceedings of the 16th Design Automation Conference
Geometric applications of a matrix searching algorithm
SCG '86 Proceedings of the second annual symposium on Computational geometry
Optimal Rotation Problems in Channel Routing
IEEE Transactions on Computers
Algorithms for routing and testing routability of planar VLSI layouts
STOC '85 Proceedings of the seventeenth annual ACM symposium on Theory of computing
On improving channel routability
ACM SIGDA Newsletter
25 years of DAC Papers on Twenty-five years of electronic design automation
Optimal Three-Layer Channel Routing
IEEE Transactions on Computers
The Number of Intersections Between two Rectangular Paths
IEEE Transactions on Computers
On Optimal Single Jog River Routing (VLSI Layout)
IEEE Transactions on Computers
Optimal river routing with crosstalk constraints
ACM Transactions on Design Automation of Electronic Systems (TODAES)
STOC '84 Proceedings of the sixteenth annual ACM symposium on Theory of computing
An approximation algorithm for manhattan routing
STOC '83 Proceedings of the fifteenth annual ACM symposium on Theory of computing
DAC '82 Proceedings of the 19th Design Automation Conference
On routing two-point nets across a channel
DAC '82 Proceedings of the 19th Design Automation Conference
An algorithm for improving optimal placement for river-routing
EURO-DAC '91 Proceedings of the conference on European design automation
Algorithms and theory of computation handbook
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We consider the problem of wiring together two parallel rows of points under a variety of conditions. The options include whether we allow the rows to slide relative to one another, whether we use only rectilinear wires or arbitrary wires, and whether we can use wires in one layer or several layers. In almost all of these combinations of conditions, we can provide a polynomial-time algorithm to minimize the distance between the parallel rows of points. We also compare two fundamentally different wiring approaches, where one and two layers are used. We show that although the theoretical model implies that there can be great gains for the two-layer strategy, even in cases where no crossovers are required, when we consider typical design rules for laying out VLSI circuits there is no substantial advantage to the two-layer approach over the one-layer approach.