On Optimal Single Jog River Routing (VLSI Layout)

Authors:
Tai-Ching Tuan
Affiliations:
-
Venue:
IEEE Transactions on Computers
Year:
1992

Citing 7
Cited 0

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Fundamentals of data structures in PASCAL
River routing in VLSI

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River routing with a small number of jogs

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Performance analysis of greedy heuristic to find a minimum total-jogs layout

Information Processing Letters
Optimal wiring between rectangles

STOC '81 Proceedings of the thirteenth annual ACM symposium on Theory of computing
Computational Aspects of VLSI

Computational Aspects of VLSI

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Abstract

The wiring problem of providing a planar rectilinear wire connection between two sets of terminals which lie on two horizontal lines in the plane is called the river routing. The problem has been widely studied. It is normally studied in conjunction with design variable(s) optimization problem. The author studies this problem when there is at most one horizontal segment in each wire. Efficient optimal algorithms are given for the following design variables: offset, separation, area, and shortest total wire length. The tight upper bound on the separation is also given.