Versatile mask generation techniques for custom microelectronic devices
DAC '78 Proceedings of the 15th Design Automation Conference
IC mask layout with a single conductor layer
DAC '70 Proceedings of the 7th Design Automation Workshop
Fast algorithms for LSI artwork analysis
DAC '77 Proceedings of the 14th Design Automation Conference
25 years of DAC Papers on Twenty-five years of electronic design automation
A compaction method for full chip VLSI layouts
DAC '93 Proceedings of the 30th international Design Automation Conference
Symbolic layout compaction review
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Minplex—a compactor that minimizes the bounding rectangle and individual rectangles in a layout
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
ACM SIGDA Newsletter
Graph-optimization techniques for IC layout and compaction
DAC '83 Proceedings of the 20th Design Automation Conference
Experiments with the SLIM Circuit Compactor
DAC '83 Proceedings of the 20th Design Automation Conference
Interactive compaction router for VLSI layout
DAC '84 Proceedings of the 21st Design Automation Conference
The rectangle placement language
DAC '84 Proceedings of the 21st Design Automation Conference
DAC '81 Proceedings of the 18th Design Automation Conference
An automatic/interactive layout planning system for arbitrarily-sized rectangular building blocks
DAC '81 Proceedings of the 18th Design Automation Conference
The node cost measure for embedding graphs on the planar grid (Extended Abstract)
STOC '80 Proceedings of the twelfth annual ACM symposium on Theory of computing
An efficient two-dimensional compaction algorithm for VLSI symbolic layout
EURO-DAC '90 Proceedings of the conference on European design automation
CACTUS: a symbolic CMOS two-dimensional compactor
EURO-DAC '90 Proceedings of the conference on European design automation
Constraint solver for generalized IC layout
IBM Journal of Research and Development
Chameleon ART: a non-optimization based analog design migration framework
Proceedings of the 43rd annual Design Automation Conference
An algorithm for optimal two-dimensional compaction of VLSI layouts
Integration, the VLSI Journal
On old and new routing problems
Proceedings of the 2011 international symposium on Physical design
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A new form of symbolic layout for integrated circuits is coupled with a mask compaction procedure which removes excess space while guaranteeing that all design rules are met. Tradeoffs between X and Y compaction are made based on critical path information. Two types of compaction are used to minimize mask area and computer run-time. Additional procedures reduce mask area by inserting jogs at strategic locations in the layout. A partitioned data base is used to store mask data in a hierarchical manner. The symbolic layout and mask compaction procedures require only 30 to 50 percent of the time traditionally needed to do equivalent hand layouts.