Minplex—a compactor that minimizes the bounding rectangle and individual rectangles in a layout

Authors:
Sching L. Lin;Jonathan Allen
Affiliations:
Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA;Research Laboratory of Electronics, Massachusetts Institute of Technology, Cambridge, MA
Venue:
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Year:
1986

Citing 6
Cited 10

CLU reference manual

CLU reference manual
A subjective review of compaction (tutorial session)

DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Improved compaction by minimized length of wires

DAC '83 Proceedings of the 20th Design Automation Conference
Virtual grid symbolic layout

DAC '81 Proceedings of the 18th Design Automation Conference
SLIM-the translation of symbolic layouts into mask data

DAC '80 Proceedings of the 17th Design Automation Conference
Computational geometry.

Computational geometry.

Unification of budgeting and placement

DAC '97 Proceedings of the 34th annual Design Automation Conference
A VLSI artwork legalization technique based on a new criterion of minimum layout perturbation

Proceedings of the 1997 international symposium on Physical design
An efficient compactor for 45° layout

DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Layout compaction for yield optimization via critical area minimization

DATE '00 Proceedings of the conference on Design, automation and test in Europe
IPRAIL: intellectual property reuse-based analog IC layout automation

Integration, the VLSI Journal - Special issue on analog and mixed-signal IC design and design methodologies
Correct-by-construction layout-centric retargeting of large analog designs

Proceedings of the 41st annual Design Automation Conference
Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting

Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Hierarchical extraction and verification of symmetry constraints for analog layout automation

Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Technology migration technique for designs with strong RET-driven layout restrictions

Proceedings of the 2005 international symposium on Physical design
Practical method for obtaining a feasible integer solution in hierarchical layout optimization

Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents a graph-theoretic compactor that minimizes the areas of the bounding rectangle and the individual rectangles in the layout. The minimization problem is formulated as a two-stage process. In the first stage, the area of the bounding rectangle is minimized, and in the second stage, the weighted sum of the areas of the individual rectangles is minimized, which automatically minimizes the lengths of the inter-connecting wires. This approach provides a general and rigorous method for wire-length minimization. Algorithms for generating and solving the constraint graph are proposed. The minimization algorithm includes a graph-theoretic Simplex method that can be used to solve minimization problems whose constraints can be expressed in terms of a directed graph.