A subjective review of compaction (tutorial session)
DAC '85 Proceedings of the 22nd ACM/IEEE Design Automation Conference
Two-dimensional compaction by “zone refining”
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Minplex—a compactor that minimizes the bounding rectangle and individual rectangles in a layout
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
DAC '84 Proceedings of the 21st Design Automation Conference
Phled45: An enhanced version of caesar supporting 45° geometries
DAC '84 Proceedings of the 21st Design Automation Conference
Transistor size optimization in the tailor layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Layout compaction with attractive and repulsive constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A hierarchy preserving hierarchical compactor
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A compaction method for full chip VLSI layouts
DAC '93 Proceedings of the 30th international Design Automation Conference
The future of custom cell generation in physical synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Diagonal routing in high performance microprocessor design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
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This paper describes a one-dimensional compactor which works efficiently on basic VLSI layout. The compactor operates on a tiled layout structure which represents any VLSI layout containing 45° multiple angles. The compaction program performs both pitch minimization and wire length minimization in either X or Y directions. The compactor works quickly and efficiently due to the clever use of the layout structure and graph based Simplex method. The compactor corrects design rule violations and preserves wire widths. It does not yet introduce jogs or compact hierarchically. Results are given for a few CMOS examples.